Dead-time control method for power electronics converters and a circuit for the application of this method

ABSTRACT

A dead time control method ( 100 ) comprising the steps of: converting the DC link voltage, output current and output voltage to digital values with an ADC (Analog to Digital converter) ( 102 ); calculating the hysteresis band for adaptive hysteresis current control using the values read by the ADC and updating the band value via recalculating it at each sampling time ( 103 ); calculating the IrefH and IrefL values using the hysteresis band and Iref ( 103   a ); generating the PWM signal by hysteresis current control ( 104 ), generating two auxiliary control signals as VP, VN ( 105 ); in the region where VP=1 and VN=0, applying of the drive signal of T 1  without setting dead time wherein T 1  is the conduction duration of an upper switch, and not applying the drive signal of T 2  wherein T 2  is the turn off duration of said upper switch and is the conduction duration of a lower switch ( 106 ).

TECHNICAL FIELD

This invention relates to a dead time control method for use in powerelectronics converters and to a circuit developed for implementation ofthis method.

PRIOR ART Brief Description of the Problem

Hysteresis current control or PWM (pulse width modulation) methods areused for current control in inverters. In the hysteresis current controlmethod, the inverter current is controlled such that it remains in theupper and lower band defined around the reference current. Dead time isset between the signals to prevent short-circuit of the elements in thephase arm in inverters. Due to the dead time set, the current extendsbeyond the hysteresis band. In this case, the current control isdisrupted.

Prior Art Practices

Dead time is set between the signals to prevent short-circuit of theelements in the phase arm in inverters. The dead time, which must be setbetween the drive signals of the semiconductor power switches, leads todisturbances in current and voltage control. Dead time compensationmethods have been developed to prevent this degradation. Dead timecompensation in PWM methods has been extensively discussed in literatureand patents. Dead time compensation stands out in inverter applicationsand improves the quality of the output voltage and current. The deadtime set between the drive signals of the upper and lower switches in aphase arm causes the inverter output voltage to be different than thedesired value according to the polarity of the current. In order toprevent this, the load ratio according to the polarity of the current,is increased or decreased in the amount of dead time in the PWMgeneration stage.

Many studies have been conducted in the context of dead time in PWMmethods. These studies are related to the dead time problem but are notdeveloped for the hysteresis current control method and therefore aredifferent from the present invention. In [1]-[3], the problem of outputcurrent and voltage waveform distortion is tried to be eliminated by adead time compensation technique. In [4], dead time compensation wasperformed with a snubber circuit. Hybrid compensation techniquesincluding feedback and feed forward are presented in [5]-[8]. In themethod proposed in [9] and [10], the dead time effect was compensatedusing the 6th harmonic component. In [11]-[16] estimation-basedapproaches are presented, in [17]-[19] the effect of dead time isstudied in predictive current control. In [20] and [21], the dead timecompensation technique was performed using parameters measured using ananalog to digital converter. In [22]-[25] the dead time compensationtechnique was performed by considering the parasitic capacity of thepower element. Pulse-based dead time compensation technique is appliedin [25]-[27]. In [28] and [29], the dead time effect is presented forthe parabolic current control method. Repetitive approaches arepresented in [30] and [31]. Vector-based in [32], ADALINE-based in [33],variable switching frequency based in [34], with adjustable compensationfactor in [35], sine PWM-based with three triangles in [36] and in [37]approaches of dynamic dead time optimization methods have beenimplemented. A dead time compensation technique using logic circuits ispresented in [38] and [39]. The method proposed in [40] is presented forlow common mode voltage. In [41], the dead time effect was tried to beeliminated by means of a simple calculation. In [42], a study was madeusing H6 topology without dead time modulation algorithm. In [43]-[46]elimination techniques are present for the dead time effect. Thesemethods eliminate the dead time effect via determining the direction ofcurrent by means of a circuit.

In the context of hysteresis current control, studies have been carriedout in the literature to keep the switching frequency constant and solvethe dead time problem. These studies were compared with the inventionproposal and no direct similarity was determined. In [47], anestimation-based method has been developed to formulate the switchingfunction with current reference, dynamic behavior and past timeinformation of the system. The method comprises a very complex hardware.Calculation is done with analog circuit. The use of many componentsincreases the cost and makes the applicability difficult and decreasethe reliability. In [48], a numerical control method is presented tokeep the frequency constant in hysteresis current control. The method isadaptive to the load parameters and the input source. The dead timeeffect is compensated by the PI controller. In [49]-[51], a numericalmethod that automatically compensates the dead time effect is used. In[52] and [53], a study was carried out for single-phase three-levelinverters. In [52], a method independent from the load parameters isproposed. This method obtains appropriate switching signals according tothe upper/lower hysteresis bandwidth, current error and switching state,to eliminate the dead time effect without dead time compensation. In[53], two techniques are presented to stabilize the frequency at thezero crossing points of the grid. These techniques are mixed-level modeland estimation-based sampling. In the mixed-level model, a transitionfrom three-level state to two-level state is made around zero.Estimation-based sampling aims to achieve the most effective switching.In [54], the effect of change in the switching frequency and samplingfrequency in the hysteresis band is analyzed. The difference between themaximum and minimum switching frequency of the fixed band hysteresiscurrent control depends on the sampling frequency of the digitalcontroller. But in here the dead time is neglected. In addition, thereare some studies for three-phase systems [55], [56]. In [55], a spacevector-based approach is presented. In [56], the average inverter outputvoltage is used as an approach to the back-emf value of the load forconstant frequency hysteresis current control. In here the dead timedelay is calculated and compensated by taking this delay into account.

There are patents granted based on dead time [57]-[61]. In [57]-[59], adead-time method for a grid-connected boosting-reducing-volage invertermode is proposed without remaining the need of using dead time. In [60],a dead time elimination method is presented using a simple logiccircuit. An upper and lower limit according to the grid voltage andwhich switching signals will be generated according to these limits aredetermined in the method [61]. Two of the four switches used for thispurpose are active at high frequency and two are active according to thepositive and negative alternans of the grid at low frequency.

In the hysteresis current control method, the current is controlledinstantaneously. The hysteresis current control is shown in a two-levelvoltage source inverter given in FIG. 1. The method can be used forapplications such as the grid-connected inverter of FIG. 1.(a) andapplications having a load such as the UPS of FIG. 1.(b). Dead time hasadverse effects on hysteresis current control method. In hysteresiscurrent control, the inductance current cannot be retained within thedefined hysteresis band due to dead time (FIG. 6). This is due to thefact that the driving signal cannot be applied immediately when thecurrent goes out of the hysteresis band and that the current continuesto travel in the same direction as much as the dead time, especially inareas where the current changes rapidly. In proportion to the dead timeset, the current extends beyond the hysteresis band and big amount ofchanges in frequency occurs.

In the simulations, it is seen that the hysteresis controller cannotkeep the inductance current in the band if dead time is set. FIG. 7shows the results for a constant band. The inductance current goes outof the lower band in the positive alternans and out of the upper band inthe negative alternans. The change in frequency is around 10 kHz. Thefrequency ranges from 2 kHz to 12 kHz.

In adaptive hysteresis current control methods, the switching frequencyis kept constant by changing the band. When this method is applied toinverters, the theoretically calculated band ensures that the frequencyis kept constant. However, due to dead time, the current exceeds thecalculated band and the frequency cannot be kept constant.

When it is aimed to keep the frequency constant at 10 kHz by applyingthe variable band, the results in FIG. 8 are obtained. In this case, theinductance current cannot be kept in the band again. The frequencyfluctuation is quite high. The frequency change obtained by simulationwhen there is no dead time is indicated by fsw_(ref). According to this,frequency control is seriously deteriorating. The dead time has anegative effect on keeping the frequency constant. The method in FIG. 5has been developed to solve this problem.

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BRIEF DESCRIPTION OF THE INVENTION

The object of the present invention is to provide a dead time controlmethod for power electronics elements and a circuit for implementingthis method.

The invention is is a dead time control method (100) for hysteresiscurrent control in power electronics converters, comprising thefollowing steps; With this method, an application circuit, comprisingswitches (T1 and T2), is controlled.

-   -   Converting the DC link voltage, output current and output        voltage to digital values with an ADC (Analog to Digital        converter) (102),    -   Calculation of the hysteresis band for adaptive hysteresis        current control using the values read by the ADC and updating        the band value by recalculating it at each sampling time (103),    -   Calculation of the IrefH and IrefL values of the upper and lower        bands of the current reference using the hysteresis band and        Iref (103 a).    -   Generating the PWM signal by hysteresis current control (104),    -   Generating two auxiliary control signals as VP, VN (105),    -   In the region where VP=1 and VN=0, a drive signal of T1 is        applied without setting dead time, and a drive signal of T2 is        not applied wherein T1 is a conduction time duration of an upper        switch and T2 is a turn off time duration of said upper switch        and the conduction time duration of a lower switch (106),    -   In the region where VP=0 and VN=1, the driving signal of T2 is        applied without setting dead time and the driving signal of T1        is not applied (107),    -   Applying the driving signals of T1 and T2 via setting dead time        in the region where VP=1 and VN=1 (108).

In this method, the hysteresis band in the step 103, i.e “Calculation ofthe hysteresis band for adaptive hysteresis current control using thevalues read by the ADC and updating the band value by recalculating itat each sampling time”, is obtained according to the formula:

h=(T_p·(m_2+m_ref)·(m_1−m_ref))/(m_1+m_2) and ΔI=h/2 wherein: T_p is theswitching period; ΔI is the hysteresis band; h is the amount offluctuation in the current; m_1 is the slope of the inductance currentwithin time t1; m_2 is the absolute value of the slope of the inductancecurrent within time t2; m_ref is the slope value of the currentreference.

In step “generating two auxiliary control signals as VP, VN (105)” ofthis method, furthermore, auxiliary control signals (VP, VN) aregenerated taking into account the regions wherein the upper and lowerband of the current reference (i.e. IrefL and IrefH) are positive andnegative,

In step “generating two auxiliary control signals as VP, VN (105)” ofthis method elsemore, the first of the auxiliary control signals (VP) isgenerated when the upper band (IrefH) is positive and the second (VN) isgenerated when the lower band (IrefL) is negative.

-   -   The invention is further a dead time control circuit (2 or 2′ or        2″) for carrying out this method (100); comprising:

a processor (10) converting the read analog values of the voltage andcurrent into digital values; calculating the hysteresis bandwidth valueand updating the bandwidth value via recalculating it in each samplingtime; generating upper and lower band values (IrefH, IrefL) via addingand subtracting the bandwidth value to/from the current reference(Iref), generating the PWM signal relative to the hysteresis band;generating two auxiliary control signals, as one of which is VP when theupper band IrefH is positive and the other is VN when the lower bandIrefL is negative and

a logic circuit and a simulation circuit (1) generating driving signalsof PWMH_ and PWML_.

This dead time control circuit (2) comprises a dead time control circuit(2); AND gate (211), transistor (222), MOSFET (223) and resistors (221).This dead time control circuit comprises 4 AND gates (211), 2 NPNtransistors (222), 1 MOSFET (223) and at least 8 resistors (221).

This dead time control circuit (2) can also be carried out equaivalentlywith other dead time control circuits. Equivalent dead time controlcircuits (2′ or 2″ or 2′″ (the alternative of 2′″ is not shown in thefigures)); is composed of with an FPGA and/or a CPLD and/or a DAC and/ora comparator and/or logic elements.

The equivalent dead time control circuit (2′ or 2″) comprises resistors(221), capacitors (225), diodes (224), and a NOT gate (212).

In this dead time control method, the signals are generated via settingdead time between the gate signals of the lower and upper switches atthe zero crossing region of the output current where the first auxiliarycontrol signal (VP) is logic 1 and the second auxiliary control signal(VN) is logic 1, and all of the power switches (T1 and T2) are switched.

In the method according to the invention, there is a processor,converting the voltage and current analog values into digital values;calculating the hysteresis bandwidth value and updating the bandwidthvalue by recalculating it in each sampling time; generating PWM signalaccording to hysteresis band; after generating the PWM signal,generating two auxiliary control signals, being the first (VP) generatedwhen the upper band IrefH is positive, being the second (VN) generatedwhen the lower band (IrefL) is negative and generating upper and lowerband values (IrefH, IrefL) via adding and subtracting the bandwidthvalue to/from the current reference (Iref).

The invention is also a circuit composed of two AND gates to which suchprocessor is connected to with a NOT gate, thereby will be used in theinput of a dead time circuit and thereby produces a rearranged PWM drivesignal (PWMH and PWML).

In this circuit, PWMH and PWML signals are generated, which are there-arranged PWM signal, as the input signal, to be PWM logic 0 when theoutput current passes the upper band (IrefH), and to be PWM logic 1 whencurrent passes the lower band (IrefL).

The invention is also a dead time control circuit for performing theaforementioned method and for connecting to the output of theaforementioned circuit. This dead time control circuit comprises 4 ANDgates, 2 NPN transistors, 1 MOSFET and resistors and generates drivingsignals (PWMH_ and PWML_) to add dead time in a power electronicsapplication circuit. In this dead time control circuit, a PWM signalgenerated in the above-described circuit is applied to the input of theMOSFET, an EN_L signal is applied to an input terminal of a first ANDgate, and an EN_H signal is applied to an input terminal of a fourth ANDgate. In this dead time control circuit furthermore;

-   -   if the PWM signal applied to the input of MOSFET is not active,        the output of all AND gates is logic 0 and this operation mode        occurs in the case where the EN_H signal applied to a terminal        of a fourth AND gate is logic 1 and the EN_L signal applied to a        terminal of a first AND gate is logic 0,    -   if the PWM signal applied to the input of MOSFET is active, the        output of all AND gates is logic 0 and this operation mode        occurs when the EN_H signal is logic 0 and the EN_L signal is        logic 1.    -   In the case where the EN_H signal is logic 1 and the EN_L signal        is logic 1, the output of a third (IC1C) AND gate becomes logic        1 with delay and the rising edge of the PWMH_drive signal is        shifted forward as long as this delay time since a first (Q2)        transistor slowly turns off while the PWM signal is active; and        when the PWM signal is passing to the passive state, a second        (Q1) transistor in conduction mode enters to a late cut off mode        and the other input of a second (IC1B) AND gate whose first        input is logic 1, becomes logic 1 with delay so that the rising        edge of the PWML_ drive signal is delayed as long as this delay        time and dead time addition is performed in the zero crossing        region of the output current.

In this dead time circuit: a first resistor (R1) is connected to thegate of the MOSFET element (M1) and a second resistor (R2) is connectedto the drain end; and the (PWM) signal is applied to the MOSFET (M1) viathe first resistor (R1); and the VCC signal is applied to the drain gateof the MOSFET (M1) via the second resistor R2; and an input pin of afirst AND gate (IC1D) is connected between the MOSFET (M1) and thesecond resistor (R2); and a third resistor (R3) is connected to theother input (shown by 13 in FIG. 3) of this first AND gate (IC1D) andthe resistor (R3) is grounded from its other end; and an EN_L signal isalso applied to this input; and the output of the first AND (IC1D) gateis connected to the first input pin of a second AND gate (IC1B) andfurther a first NPN transistor (Q2) is connected to the output of thefirst AND gate via another resistor (R5); and the collector terminal ofthis transistor (Q2) is supplied with VCC voltage by another resistor(R7) and the emitter terminal is grounded; and a first input of a thirdAND gate (IC1C) is connected to the collector terminal of this firsttransistor (Q2); and on the other hand a PWM signal is applied to thefirst pin of a fourth AND gate (IC1A) and the EN_H signal is applied tothe second pin; and the second pin is further connected to ground byanother resistor (R4); and the second input pin of the third AND gate(IC1C) is connected to the output of this fourth AND gate, and a secondNPN type transistor (Q1) is connected to this output via anotherresistor (R6); and the collector of this second transistor (Q1) is alsoconnected to the Vcc voltage by another resistor (R8), and the emitterof this second transistor (Q1) is also connected to ground; and thesecond input pin of the second AND gate (IC1B) is connected to thecollector of this second transistor (Q1); and in this circuit, theoutput of the third AND gate represents the PWMH_ signal, ie the drivingsignal to be applied to a power electronic switch in an applicationcircuit; and the output of the second AND gate represents another drivesignal PWML_ to be applied to another switch in the same applicationcircuit.

The invention is also an other dead time control circuit, using theaforementioned PWMH signal wherein the above-described method (100) isused, wherein this circuit consists of the following for the applicationof this method: a parallel connected resistor and diode (224) group ofwhose input is applied with PWMH signal and whose output is connectedboth to a capacitor and to a “+” end of a comparator; the “−” end isconnected to a power supply of such comparator, an AND gate of whose onepin is connected to the output of the comparator via a NOT gate, theother pin is connected to the PWML signal and a PWML_ signal is receivedfrom this AND gate and also for setting dead time to a rising edge of agate signal in the power electronics application circuit, when PWMH isactive in this circuit, capacitor charges over diode fastly, when PWMHis not active, it discharges over resistor slowly; PWML_ signal is notgenerated until the voltage value of the capacitor drops below thevoltage source value connected to the negative input of the comparatorwhile the capacitor is discharged and therefore the rising edge of thePWML signal is delayed as duration of dead time.

The invention is also an other dead time control circuit, using theaforementioned PWMH signal wherein the above-described method (100) isused, wherein this circuit consists of the following for the applicationof this method: a parallel connected resistor and diode (224) group ofwhose input is applied with PWML signal and whose output is connectedboth to a capacitor and to a “+” end of a comparator; the “−” end isconnected to a power supply of such comparator, an AND gate of whose onepin is connected to the output of the comparator via a NOT gate, theother pin is connected to the PWMH signal and a PWMH_ signal is receivedfrom this AND gate and also for setting dead time to a rising edge of agate signal in the power electronics application circuit, when PWML isactive in this circuit, capacitor charges over diode fastly, when PWMLis not active, it discharges over resistor slowly; PWMH_ signal is notgenerated until the voltage value of the capacitor drops below thevoltage source value connected to the negative input of the comparatorwhile the capacitor is discharged and therefore the rising edge of thePWMH signal is delayed as duration of dead time.

Thanks to the developed dead time method, problems of overflow of thecurrent due to dead time and inability to keep the frequency constantare largely solved. The developed method is very simple and can beeasily implemented with digital or analog circuits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1: are topological views of the circuit.

FIGS. 1a and 1b : topological views of the circuit of which the subjectmethod of the invention is applied in two different embodiments. Theinvention is applied to two level voltage sourced inverter in theseembodiments (Application circuit).

FIG. 2: is the schematic diagram showing the generation of pulse wideregulated signals and the application of generated signals to a deadtime control circuit in the circuit subject to invention. The signals ofwhich the pulse wide is regulated are: the signals of PWM (Pulse-WidthModulation), EN_L (i.e.: VN) and EN_H (i.e.: VP). With this circuit thesignals of PWMH (Pulse-Width Modulation High), PWML (Pulse-WidthModulation Low) are generated as well.

FIG. 3: is the dead time control circuit according to the invention.

FIG. 4: are the dead time control circuits.

FIGS. 4a and 4b : are the other dead time control circuits in which thesubject method of the invention is applied.

FIG. 5: is the flow chart of the dead time control method according tothe invention.

FIG. 6: is the graph showing the driving signals and current change inthe hysteresis current control method in the conventional method in theprior art.

FIG. 7: is a graph showing the state that the current cannot be retainedin the band due to the effect of dead time when a constant hysteresisband is used in the conventional method (in the prior art), that is, thestate where the current flows out from the band.

FIG. 8: In the conventional method (in the prior art), when the adaptive(i.e. variable) hysteresis band is used, it is the graph showing thestate that the current cannot be retained within the band i.e. the statethat the current flows over the band due to the dead time effect.

FIG. 9: The variable definitions for the controlling of hysteresiscurrent control with constant frequency.

FIG. 10: Generation of VP and VN auxiliary control signals.

FIG. 11: When fsw_ref=10 kHz, it is the simulation results while deadtime prevention is active.

DESCRIPTION OF THE REFERENCES IN THE FIGURES

For comprehensibility of the invention, the parts in the attachedfigures have been individually numbered and corresponding definitionsare provided below.

-   -   1. Invention circuit    -   2. Dead time control circuit    -   2′ Dead time control circuit    -   2″ Dead time control circuit    -   3. Application circuit    -   10. Processor        -   121. Comparator        -   122 DAC        -   123 Flip Flop    -   211 AND gate    -   212 NOT gate    -   221 Resistor    -   222 Transistor    -   223 MOSFET    -   224 Diode    -   225 Capacitor    -   226 Comparator    -   Y: Load    -   V_(s): Grid voltage    -   L_(f): Filter inductance of inverter output    -   C_(f): Filter capacitor    -   L_(s): Filter inductance of the grid    -   D₁ and D₂: Diodes    -   T₁ and T₂: Switches    -   ADC: An Analog-Digital Converter    -   CAP: CAPTURE unit    -   DSP: Digital Signal Processing unit    -   Analog HCC: Analog Hysteresis Current Control    -   100. Dead time control method

DETAILED DESCRIPTION OF THE INVENTION

An invention circuit (1) and a dead time control circuit (2 or 2′) areused in the method according to the invention. PWM, PWMH, PWML and EN_L,EN_H signals, which are going to be used at the input of the dead timecircuit (2 or 2′), are generated with the invention circuit (1). On theother hand, PWMH_ and PWML signals, which are going to be applied topower electronics converters, for example to a two level voltage sourcedinverter, are generated in the dead time circuit (2 or 2′).

Application circuit (3) comprises a diode (D₁) to which an upper switch(T₁) is parallel connected and a diode (D₂) to which a lower switch (T₂)is parallel connected. At the output of the application circuit (3).which is a two level half bridge inverter topology, grid voltage (V_(s))and filter components (L_(f), C_(f), L_(s)) as to be filter inductanceof inverter output (L_(f)), filter capacitor (C_(f)) and filterinductance of the grid (L_(s)) are provided. Ground of the grid voltage(V_(s)) is connected to the middle point of DC link capacitors (225)which are serial connected at the input. DC input voltage is convertedto AC voltage (V_(o)) at the output via power elements. V_(o) voltage ofthe output of the inverter, which is in the form of square wave, isconverted into sinusoidal form with filter elements and the energy istransmitted to grid voltage (V_(s)).

Invention circuit (1) is composed of a processor (10) and two AND gates(211) to which the processor (10) is connected with a NOT gate (212).

The processor (10) comprises an analog and a digital part. DigitalSignal Processing (DSP) and digital control is provided at the digitalpart. The processor (10) comprises at least one comparator (121), atleast one DAC (Digital-Analog Converter) (122) and at least one FlipFlop (123). The analog part comprises two comparators (121) and an SRflip flop (123) connected to these comparators (121). The analog part isthe section realizing analog HCC in the processor. Controlling of thephase arm is provided with the analog part. The PWM signal comes fromthe output of the SR flip flop (123). EN_H (VP) and EN_L (VN) signalsare generated via calculating hysteresis band in the processor (10).Driving signals (PWMH_ and PWML_) which is stated in the method isprovided at the output of the dead time circuit (2, 2′ and 2″).Developed dead time circuit can be applied not only with analog elementsbut also can be provided using FPGA (Field Programmable Gate Array) orCPLD (Complex Programmable Logic Device).

Dead time control circuit (2) comprises 4 AND gates (211), 2 NPNtransistors (222), 1 MOSFET (223) and resistors (221). In this circuit(2); a first resistor (R1) (221) is connected to the gate port of theelement MOSFET (223) (M1) and a second resistor (R2) (221) is connectedto the drain port of the MOSFET (223) (M1). PWM signal is applied to theMOSFET (M1) (223) via the first resistor (R1). VCC signal is applied tothe drain port of the MOSFET (M1) (223) via the second resistor (R2)(221). One input pin (Indicated with the number 12 in FIG. 3) of a firstAND gate (IC1D) (211) is connected in between MOSFET (M1) (223) and thesecond resistor (R2). A third resistor (R3) (221) is connected to theother input pin (indicated with the number 13 in FIG. 3) of this firstAND gate (IC1D) (211) and resistor (R3) (221) is grounded from its otherend. Furthermore, EN_L signal is applied to this input pin (13). Firstinput pin (4) of a second AND gate (IC1B) (211) is connected to theoutput of this first AND gate (IC1D). Also a first NPN transistor (Q2)(222) is connected to the output of the first AND gate (211) via anotherresistor (R5) (221). VCC voltage is given to collector terminal of thistransistor (Q2) (222) via yet another resistor (R7) (221). Emitterterminal is grounded. First input pin (10) of a third AND gate (IC1C)(211) is connected to the collector terminal of this first transistor(Q2) (222).

On the other hand, in this circuit (2), PWM signal is applied to thefirst pin (1) of a fourth AND gate (IC1A) (211). EN_H signal is appliedto the second pin (2) as well. This second pin is also connected to theground via another resistor (R4) (221). Second input pin (9) of thethird AND gate (IC1C) is connected to the output (3) of this fourth ANDgate (211). Also a second NPN type transistor (Q1) (222) is connected tothis output (3) via another resistor (R6) (221). Collector of thissecond transistor (Q1) (222) is connected to VCC voltage via againanother resistor (R8) (221). Emitter of this second transistor (Q1)(222) is again connected to the ground. Second input pin (5) of thesecond AND gate (IC1B) (211) is connected to the collector of thissecond transistor (Q1) (222).

In this circuit (2), the output (8) of the third AND gate (211)represents PWMH_ signal. The output (6) of the second AND gate (211)represents PWML_ signal. These two signals (PWMH_ and PWML_) are appliedas the gate signals (gate signals of T₁ and T₂ switches of FIG. 1) tothe power electronics element (for example two level voltage sourcedinverter) of the application circuit (3) (FIG. 1).

Numerations of input and output pins of the elements presented in thedead time circuit (2″) of FIG. 3, are independent from the referencespresented above in the parts list.

In FIG. 3, PWM, EN_L (i.e. VN) and EN_H (i.e. VP) signals are generatedin the processor (10). After producing signals with the processor (10),the dead time control circuit (2″) works as follows: In the state ofEN_H(VP) signal is active and EN_L(VN) signal is passive (i.e. the majorpart of positive half period of output current), before being used ofthe dead time circuit (2) as the invention circuit, when PWM signalgenerated in the processor (10) is active, MOSFET (223) turns on andboth input signals of the AND gate (IC1D) (211), using EN_L signal asinput, become logic 0 as well. Therefore, the output of this AND gate(IC1D) (211) is 0. As a result of this, the transistor Q2 (222) remainsin cut off mode and one input of the AND gate (IC1C) (211) becomeslogic 1. On the other hand, since the output of the IC1D which is logic1, is directly used as input of IC1B, one input of the IC1B becomeslogic 1 as well, wherein IC1D is the first AND gate (211) and IC1B isthe second AND gate (211). And now if we turn to the AND gate (211) inthe name of IC1A: since PWM is active, one input of this AND gate (211)is logic 1 and its other input is logic 1 since EN_H is active. As aresult, the output of IC1A is logic 1. Therefore, HX is also logic 1 andthe output of the IC1C is high since both two inputs of the third ANDgate (211) in the name of IC1C is logic1, and this signal is used as thegate signal of upper switch of the two level inverter. On the otherhand, since the output of the AND gate (211) in the name of IC1A islogic 1, the transistor Q1 (222) turns on and the other input of the ANDgate (211) in the name of IC1B becomes logic 0. Thus, the output of theAND gate IC1B is logic 0 and signal is not applied to the lower switchof the two level inverter. If PWM signal is not active, output of allAND gates (211) are logic 0 and the gate signals (gate signals of T₁ andT₂ switches in FIG. 1) are not active. This working principle realizesin the case of EN_H=1 and EN_L=0.

Let's examine the case of EN_H=0 and EN_L=1 (i.e. the major part ofnegative half period of the output current). If the PWM signal is notactive, both inputs of AND gate IC1D (211) are logic 1 and the output ofthis AND gate (211) becomes logic 1. As a result, the transistor Q2(222) turns on and one of the inputs of the AND gate IC1C (211) becomeslogic 0. IF the other input of the AND gate (211) IC1C (211) is named asHX, this HX input is logic 0, since the output of the AND gate IC1A(211) is logic 0. Thus, at the output of the AND gate IC1C (211), logic0 signal is provided. This signal is the signal of upper switch (T₁) ofthe inverter and this means the gate signal (PWMH_) of the upper switch(T₁) is not active. On the other hand, since output of the AND gate IC1A(211) is logic 0, the transistor Q1 (222) is in cut off and one input ofthe AND gate IC1B (211) becomes logic 1. If the other input of the ANDgate IC1B (211) is named as LX, this LX input is also logic 1, since theoutput of the AND gate IC1D (211) is logic 1. As a result, the output ofthe AND gate IC1B (211) becomes logic 1 and in this case, gate signal(PWML_) of the lower switch (T₂) of the inverter becomes active. IF PWMsignal becomes active, output of the all AND Gates (211) become logic 0and in this case, gate signals of none of the switches will not beactive. This working principle realizes in the case of EN_H=0 andEN_L=1.

Finally let's examine the case of EN_H=1 and EN_L=1 (i.e. around thezero crossing zone of the output current) In here we should statespecifically the following situation. Since getting the Q1 and Q2transistors (222) in the cutoff mode are slow, this function is used asadding dead time in the present invention. If we clarify workingprinciple for this range: if PWM signal is active, MOSFET (M1) (223)turns on and one input of the AND gate IC1D (211) becomes logic 0. As aresult, the output of the AND gate IC1D is logic 0. Since both twoinputs of the AND gate IC1A (211) is logic 1, its output is logic 1. Ifthe PWM signal is not active, MOSFET (M1) (223) gets in cut-off stateand both two inputs of the AND gate IC1D (211) are logic 1 and itsoutput is logic 1. As to one input of the AND gate IC1A (211) is logic0, the output of it, is logic 0. Active and passive states of PWM signalresults in as such. One more time, let's check the active state of PWMsignal. The condition of being active of the PWMH_ signal, to be appliedto the upper switch (T₁) in the inverter of FIG. 1, is possible when thetwo inputs of the AND gate IC1C (211) are logic 1. In here, thecondition of adding dead time for PWMH_ signal, is provided using thecharacteristic of transistor Q2 (222) which gets into cut-off stateslowly wherein the transistor Q2 (222) was in conduction state before.Since the transistor Q2 (222) gets into cut-off state slowly, the outputof the AND gate IC1C (211) becomes logic 1 with delay and the risingedge of PWMH_ signal is delayed forwardly as long as the duration ofthis delay time. Likewise, when the PWM signal passes into passivestate, the transistor Q1 (222) which is in conduction state, will turnoff lately and the other input of AND gate IC1B (211), whose one inputis logic 1, will become logic 1 with delay. Therefore, the rising edgeof PWML_ signal will be delayed as long as this delay. Thus, process ofadding dead time of the output current, at the zero crossing zone isprovided in this way.

The method subject to invention (100) works as following steps.

-   -   Reading the DC link voltage, output current and grid voltage by        sensors (101),    -   Converting the analog voltage and current values that are read        to digital values with an ADC (102),    -   Calculation of the hysteresis band by digital part of the        processor (10) for adaptive hysteresis current control and        updating the band value at each sampling time (103),    -   Calculation of the IrefH and IrefL values using the hysteresis        band and Iref (103 a),    -   Generating of the PWM signal by digital part of the processor        (10) according to the hysteresis band (104),    -   After generating PWM signal, generating two auxiliary control        signals taking into account of the positive and negative regions        of the lower and upper bands (IrefL and IrefH) of the current        reference, i.e. generating the first one of the auxiliary        control signals (VP) when upper band (IrefH), is in positive        state and generating the second one of the auxiliary control        signals (VN) when lower band (IrefL) is in negative state (105),    -   Not applying negative signal in the region where current (Iref)        is positive and thereby without applying dead time, only        applying positive signal without delay (106).    -   Likewise, not applying positive signal in the region where        current (Iref) is negative and thereby, only generating negative        signal without dead time (107),    -   In the region where first auxiliary control signal (VP) is logic        1 and second auxiliary control signal (VN) is logic 1 and when        upper band (IrefH) of the current is positive and lower band of        the current is negative, generating signals via setting dead        time between upper and lower signals and switching all the        switches (T₁ and T₂) (108).

The steps of 102, 103, 104, 105 are processed by processor (10) in themethod (100) subject to invention.

Furthermore, frequency is measured via reading the PWM signal by CAPTURE(CAP) unit in the method (100) subject to invention.

The process of measuring the frequency via reading the PWM signal by aCAPTURE (CAP) unit is executed for measuring the frequency and to seethe result of the method.

In the step of 103, 2 comparators (121), a DAC (Digital AnalogConverter) (122) and 1 SR flip flop (123) are used for applying adaptivehysteresis current control. In the preferred embodiment, thesecomponents are located in the processor (10). The step 103 is executedby the processor (10). How the calculation of the step 103 is provided,is defined below:

In order to solve the variable frequency problem of classical hysteresiscontrol, it is a must to control the band. So as to make the switchingfrequency constant, the requirement for controlling the band isdescribed on the FIG. 9.

The band value providing the switching frequency to be constant, isobtained mathematically using definitions indicated in FIG. 9. Thevariables used in the band calculation are listed below:

T_(p): Switching period

t₁: conduction duration of the upper switch

t₂: turn off duration of the upper switch and conduction duration of thelower switch at the same time

Δi₁: the increase of the inductance current in t₁ time

Δi₂: the decrease of the inductance current in t₂ time

$\frac{{di}^{*}}{dt}\text{:}$

derivative of reference of current

Δi₁: the increase of the reference of current in t₁ time

Δi₂: the increase of the reference of current in t₂ time

ΔI: Hysteresis band

h: Fluctuation amount in current

m₁: slope of inductance current in t₁ time

m₂: absolute value of slope in inductance current in t₂ time

m_(ref): slope of current reference

In order to find h value for a constant period/frequency; in theequilibrium of T_(p)=t₁+t₂; t₁ and t₂ time can be written in terms ofm₁, m₂ and m_(ref) slopes and circuit parameters. The increase amount inthe inductance current in t₁ range is obtained as follows:

Δi ₁ =h+Δi ₁*  (1)

$\begin{matrix}{{\Delta\; i_{1}} = {{\frac{{di}_{L}}{dt}t_{1}} = {m_{1}t_{1}}}} & (2) \\{m_{1} = {\frac{V_{L}( t_{1} )}{L} = \frac{V_{dcP} - V_{s}}{L}}} & (3)\end{matrix}$

The change amount of the current reference in t₁ range is found asfollows:

$\begin{matrix}{{\Delta\; i_{1}^{*}} = {{\frac{{di}^{*}}{dt}t_{1}} = {m_{ref}t_{1}}}} & (4)\end{matrix}$

The following equilibriums are obtained using the equilibriums (1) and(4).

$\begin{matrix}{{m_{1}t_{1}} = {h + {m_{ref}t_{1}}}} & (5) \\{t_{1} = \frac{h}{m_{1} - m_{ref}}} & (6)\end{matrix}$

A similar way is used for obtaining t₂.

$\begin{matrix}{h = {{\Delta\; i_{2}} + {\Delta\; i_{2}^{*}}}} & (7) \\{{\Delta\; i_{2}} = {{\frac{{di}_{L}}{dt}t_{2}} = {m_{2}t_{2}}}} & (8) \\{m_{2} = {{- \frac{V_{L}( t_{2} )}{L}} = \frac{V_{dcN} + V_{s}}{L}}} & (9)\end{matrix}$

Is obtained. The change amount of the current reference in t₂ range isas follows:

$\begin{matrix}{{\Delta\; i_{2}^{*}} = {{\frac{{di}^{*}}{dt}t_{2}} = {m_{ref}t_{2}}}} & (10)\end{matrix}$

Via using (7), (8) and (10):

$\begin{matrix}{h = {{m_{2}t_{2}} + {m_{ref}t_{2}}}} & (11) \\{t_{2} = \frac{h}{m_{2} + m_{ref}}} & (12)\end{matrix}$

Is obtained. Total period is calculated using the equilibriums (6) and(12).

$\begin{matrix}{T_{p} = {t_{1} + t_{2}}} & (13) \\{T_{p} = {\frac{h}{m_{1} - m_{ref}} + \frac{h}{m_{2} - m_{ref}}}} & (14)\end{matrix}$

From here, hysteresis band for a constant period is:

$\begin{matrix}{h = \frac{T_{p} \cdot ( {m_{2} + m_{ref}} ) \cdot ( {m_{1} - m_{ref}} )}{m_{1} + m_{2}}} & (15)\end{matrix}$

obtained as ΔI=h/2. Via adding this obtained band value to the currentreference, the upper band value is obtained; and via deducting thisobtained band value from the current reference, the lower band value isobtained.

A processor unit (10), for example a microprocessor can be used in thestep 104, for generating PWM signal.

Control signals generated in the step 105 are indicated in FIG. 10 as VPand VN signals.

After generating PWM signal in the step 105 in the method (100) subjectto invention, firstly two auxiliary control signal are produced as VPand VN showed in FIG. 10, taking into account the regions wherein lowerband (IrefL) and upper band (IrefH) of the current reference arepositive and negative. VP signal represents the positive state of theupper band (IrefH). In other words, the signal VP is the signal which islogic 1 when the upper band is positive and logic 0 when the upper bandis negative. VN signal represents the negative state of the lower band(IrefL). In other words, the signal VN is the signal which is logic 1when the lower band is negative and logic 0 when the lower band ispositive. The aim of these signals is not applying negative signal inthe region where the current is positive and thereby only applyingpositive signal without setting dead time and without delay. Likewise,positive signal will not be applied in the region where current isnegative, only negative signal will be generated without dead time. Inother words, when the upper current reference (IrefH) is positive, dueto the reason that only upper switch (T₁) and lower diode (D₂) will bein conduction, dead time is not added to the signal of upper switch (T₁)and signal is not applied to the lower switch (T₂). Likewise, when thelower current reference (IrefL) is negative, due to the reason that onlylower switch (T₂) and upper diode (D₁) will be in conduction, dead timeis not added to the driving signal of lower switch (T₂). When upper bandof the current (IrefH) is positive and the lower band (IrefL) of it isnegative, the signals are generated via setting dead time in betweenlower and upper signals. Thanks to the dead time generated in this way,overflowing outside the band is prevented and holding the frequencyconstant is possible.

If the signal of the current becomes both positive and negative withinthe switching period, dead time will be set between the signals and bothswitches will be switched. This region (i.e., the region where VP=logic1 and VN=logic 1, or the region in which the EN_H=logic 1 and EN_L=logic1 in the dead time circuit (2) according to the invention) correspondsto the region where the current change is not very fast. Therefore, nosignificant overflow occurs in this range and the last generated gatesignals are applied to the switches (T₁ veT₂). (It is applied to theoutput of the dead time circuit (2, 2, 2″) of FIG. 3 or FIG. 4 and tothe application circuit (3) of FIG. 1.

In the present invention, the processor (10) further generates VP and VNsignals and upper (IrefH) and lower (IrefL) band values. These upper andlower band values (IrefH, IrefL) are obtained by adding and subtractingthe bandwidth value to the current reference (Iref) wherein thebandwidth value is found by calculation. In adaptive hysteresis currentcontrol, this band value is calculated and updated at each samplingperiod. Thus, a variable band value is obtained within one period of thecurrent reference. Thus, the frequency is kept constant. The methodaccording to the invention can also be applied to constant hysteresisband current control. However, since the frequency is desired to beconstant in the applications, adaptive hysteresis current control withconstant frequency is sampled in this specification. The analog part ofthe processor is the unit which performs the classical hysteresiscurrent control. When the output current passes the upper band (IrefH),PWM becomes 0 (PWM=0) while PWM becomes 1 (PWM=1) when the currentpasses the lower band (IrefL). Thus, VP, VN and PWM signals aregenerated by processor (10). PWMH and PWML signals are obtained thanksto the method of the invention. However, in the zero crossing region ofthe output current, both VP and VN become logic 1. In this case, boththe upper (T₁) switch and the lower (T₂) switch are actively used in theapplication circuit (3). In this case, dead time must be added to therising edges of the switches. However, this dead time has no adverseeffect on the method of the invention in current control.

In the other dead time circuits (2′ and 2″) (which are also used in thesimulation) to which the method (100) is applied, the dead time additionprocess to the rising edge of the gate signal is performed with thestructure composed of resistor (221), capacitor (225) and diode (224).Equivalent two different dead time circuit (2′ and 2″) are used forupper and lower switches.

The dead time circuit (2′) of FIG. 4-a comprises a parallel connectedresistor (221) and a diode (224). PWMH signal is applied to this group.The output of the group consisting of this resistor (221) and diode(224) is connected to both a capacitor (225) and the + end of acomparator (226). The − end of the comparator (226) is connected to apower source. The power supply is grounded. The output of the comparator(226) is connected to a NOT gate (212) and the output of the NOT gate(212) is connected to an input of an AND gate (211). The other input ofthis AND gate (211) is provided with a PWML signal. The PWML_ signal isreceived from the output of this AND gate (211).

The dead time circuit (2″) of FIG. 4-b comprises a resistor (221) and adiode (224) connected in parallel. PWML signal is applied to this group.The output of the group consisting of this resistor (221) and diode(224) is connected to both a capacitor (225) and the + end of acomparator (226). The − end of the comparator (226) is connected to apower source. The power supply is grounded. The output of the comparator(226) is connected to a NOT gate (212) and the output of the NOT gate(212) is connected to an input of an AND gate (211). The PWMH signal isprovided to the other input of this AND gate (211). The PWMH_ signal isreceived from the output of this AND gate (211).

The dead time circuit (2′) in FIG. 4-a works as follows: The PWML_signal is applied to the lower switch (T₂) in the application circuit(3). In order of this signal to be active, both inputs of the AND gatewith the number 211 (211) must be logic 1. PWML refers to a signalwithout dead-time. Our aim is to shift the rising edge of this signal asthe duration as dead time. So this signal is already logical 1. For theother input of AND gate (211) to be logic 1, the output of comparator(226) must be active. There is a constant voltage supply in the negativeinput of comparator (226). The positive input of comparator (226) is thevoltage of the capacitor (225). This capacitor is rapidly charged viadiode (224) when PWMH is active, and slowly discharged via resistor(221) when PWMH is not active. While the capacitor (225) is discharged,the PWML_ signal is not generated until the voltage value of thecapacitor (225) falls below the value of the voltage source connected tothe negative input of the comparator (226). Thus, the rising edge of thePWML signal is delayed as long as the dead time. A similar process isperformed in the other dead time circuit (2″) of FIG. 4-b to generatethe PWMH_ signal. As a result, the gate signals of the switches (T₁, T₂)are thus obtained.

When there is no dead time, the frequency change obtained by simulationis indicated by fsw. The received simulation results are indicated inFIG. 11 in the case when the desired reference switching frequency as tobe constant, in other words the frequency at which the user wants towork is fsw_ref=10 kHz and when the dead time method is active. In here,the fluctuation in the switching frequency appears to be very low. Inthis embodiment, the method (100) is applied to two-level single-phasevoltage sourced inverters. It has been shown that dead time problems aresignificantly reduced by this way. The developed method (100) can alsobe applied to three-level inverters and other power electronicsconverters.

The invention is not limited to the embodiments described above, and theperson skilled in the art can easily introduce different embodiments ofthe invention. They should be considered within the scope of theinvention as claimed by the claims.

1. A dead time control method to keep the switching frequency constant,for hysteresis current control in power electronics converters,comprising the steps (100) of; converting the DC link voltage, outputcurrent and output voltage to digital values with an ADC (Analog toDigital converter) (102); calculating the hysteresis bandwidth value foradaptive hysteresis current control using the values read by the ADC andupdating the bandwidth value by recalculating it, in each sampling time(103), calculation of the IrefH and IrefL values of the upper and lowerbands of the current reference using the calculated hysteresis bandwidthvalue of the step 103 and Iref (103 a), generating the PWM signal byhysteresis current control (104), generating two auxiliary controlsignals as VP, VN (105), wherein in this step (105) these auxiliarycontrol signals (VP, VN) are generated taking into account the regionsin which the lower and upper band of the current reference (i.e. IrefLand IrefH) are positive and negative, applying, in the region where VP=1and VN=0, the drive signal of T₁ without setting dead time and notapplying the drive signal of T₂ wherein T₁ is the conduction duration ofan upper switch and T₂ is the turn off time of said upper switch and isthe conduction duration of a lower switch, (106), applying, in theregion where VP=0 and VN=1, the driving signal of T₂ without settingdead time and not applying the driving signal of T₁ (107), and applyingthe driving signals of T₁ and T₂ by setting dead time in the regionwhere VP=1 and VN=1 (108).
 2. The method (100) according to claim 1,wherein the hysteresis bandwidth is calculated in step “Calculating thehysteresis bandwidth value for adaptive hysteresis current control usingthe values read by the ADC and updating the bandwidth value byrecalculating it, in each sampling time (103)”, according to the formulaof:$h = \frac{T_{p} \cdot ( {m_{2} + m_{ref}} ) \cdot ( {m_{1} - m_{ref}} )}{m_{1} + m_{2}}$and ΔI=h/2 wherein T_(p) is the switching period, ΔI is the hysteresisband, h is the amount of fluctuation in the current, m₁ is the slope ofthe inductance current within time t1, m₂ is the absolute value of theslope of the inductance current within time t2; m_(ref) is the slopevalue of the current reference.
 3. The method (100) according to claim1, wherein the upper and lower bands of the current reference (IrefH andIrefL) in the step “Calculation of the IrefH and IrefL values of theupper and lower bands of the current reference using the calculatedhysteresis bandwidth value of the step 103 and Iref (103 a)”, arecalculated via adding the calculated bandwidth value to the currentreference to obtain the upper band value; and via deducting thecalculated bandwidth value from the current reference, to obtain thelower band value.
 4. The method (100) according to claim 1, wherein thefirst of the auxiliary control signals (VP) is generated in case theupper band (IrefH) is positive and the second of the auxiliary controlsignals (VN) is generated in case the lower band (IrefL) is negative inthe step (105) of generating two auxiliary control signals VP, VN.
 5. Adead time control circuit (2 or 2′ or 2′) for application of a method(100) according to claim 1, comprising a processor (10) converting theread analog values of the voltage and current into digital values;calculating the hysteresis bandwidth value and updating the bandwidthvalue via recalculating it in each sampling time; generating upper andlower band values (IrefH, IrefL) using the calculated hysteresisbandwidth via adding and subtracting the hysteresis bandwidth valueto/from the current reference (Iref), generating the PWM signal relativeto the hysteresis bandwidth; generating two auxiliary control signals,as one of which is VP when the upper band IrefH is positive and theother is VN when the lower band IrefL is negative and a logic circuitand a simulation circuit (1) generating driving signals of PWMH_ andPWML_.
 6. The dead time control circuit (2) according to claim 5,comprising and gate (211), transistor (222), MOSFET (223) and resistors(221).
 7. The dead time control circuit (2′ or 2″) according to claim 5,which is composed of FPGA and/or CPLD and/or DAC and/or comparatorand/or logic elements.
 8. The dead time control circuit (2′ or 2″)according to claim 5, comprising resistors (221), capacitor (225),diodes (224) and a NOT gate (212).
 9. The dead time control circuit (2)according to claim 5, comprising 4 and gates (211), 2 NPN transistors(222), 1 MOSFET (223) and at least 8 resistors (221).